The disclosure relates generally to forming FinFETs, and more particularly, to a p-type FinFET and method of forming a source/drain extension region therefor in a high percentage germanium-including fin.
Integrated circuit (IC) formation continues to occur at ever smaller dimensions. Current technology is focused on the 10 nanometer technology node. One challenge for the 10 nanometer technology node and beyond is presented by material changes in the semiconductor structures used to make the ICs. For example, advanced technology nodes are turning to different materials for fins that are used to form fin-type field effect transistors (FinFETs). FinFETs use relatively tall, thin semiconductor fins to form the requisite parts of the FET. For example, with FinFETs, a gate is formed over a semiconductor fin to create a channel thereunder in the fin, and doped source/drain (S/D) regions are provided by doping portions of the semiconductor fin that extend from sides of the gate. S/D regions may have doped extensions that extend into the channel under the gate. The form of dopants used depends on the type of FinFET desired: n-type or p-type. N-type elements introduced to a semiconductor generate free electrons (by “donating” electron to semiconductor), and P-type elements introduced to a semiconductor generate free holes (by “accepting” electron from semiconductor atom and “releasing” hole at the same time). P-type FETs operate on a depletion-mode in which a positive charge from a gate forces positively charged holes away from the gate-insulator/semiconductor contact area (depleting area), leaving exposed a carrier-free area of negatively charged, immobile, acceptor ions.
For p-type FinFETs, current technology nodes and beyond are using high percentage germanium-including fins such as relaxed (not strained) silicon germanium (SiGe) having 75% or greater germanium (Ge) content—up to pure Ge (i.e., 100% Ge). For pFinFETs, typically the higher the germanium percentage in the channel of the germanium-including fin, the better the performance in terms of hole mobility, compared to silicon alone. One challenge with this material is that junction formation in pFinFETS (i.e., formation S/D region extensions into a channel under the gate) is accomplished by out-diffusion of p-dopant (commonly boron) from a source/drain merge epitaxy layer provided over the source/drain region of the fin and into the channel under a spacer of the gate. The more abrupt the junction between the channel of the germanium-including fin and the source/drain region (and extension), the better the performance. Ion implantation has been used in earlier technology nodes to implant boron into the epitaxy layer, which is then followed by annealing to diffuse the boron. However, ion implantation is becoming impractical due to the tight dimensions and the three-dimensional structures of advancing FinFET architecture. More troubling, boron diffusion is significantly reduced the higher the germanium content of the germanium-including fins—practically no diffusion of boron occurs in pure germanium. Consequently, obtaining the best performance becomes a tradeoff between high germanium content in the channel and better boron diffusion for the source/drain regions.